1. Field of the Invention
The present invention relates to an integrated circuit device and, particularly, to power control of an integrated circuit.
2. Description of Related Art
Various types of large scale integrations (LSI) are incorporated in mobile phones and mobile terminals that are driven by a battery. Reduction of power consumption in LSI is very important factor to enable long time use and achieve multifunction of mobile phones and so on. Further, as LSI becomes more complex, the proportion of static consumption current or leakage current that is consumed in stop state to entire consumption current rises so high that it is not negligible in a microfabrication process of 0.13 μm or less.
In order to reduce leakage current, there is proposed a technique that divides the inside of LSI into a plurality of blocks and supplies power individually to each block, thereby stopping power supply to the block that is not necessary for operation.
A conventional power control technique is described hereinafter with reference to FIG. 6. As shown in FIG. 6, LSI 100 is connected to a power IC 200. The LSI 100 has a central processor unit (CPU) 10, a constant power-on region 20, a logic circuit A 30, and a logic circuit B 40. The constant power-on region 20 is a circuit region to which power is supplied constantly in spite that other circuits such as the CPU 10 are not operating. The constant power-on region 20 has a control circuit 21 that controls power supply of the CPU 10. The control circuit 21 is implemented by a hardware fixed circuit composed of an electric circuit that does not use program and merely executes a fixed operation such as a simple power-on request, for example. The power IC 200 is a functional block that has a power supply section 201 for the logic circuit A 30, a power supply section 202 for the CPU 10, a power supply section 203 for the constant power-on region 20, a power supply section 204 for the logic circuit B 40, a control interface (I/F) 205, and a power-on request processing section 206 for the CPU 10.
A processing operation where an external interrupt signal is input to the control circuit 21 when power supply to the CPU 10 is shut off in the conventional technique shown in FIG. 6 is described hereinafter. Detecting the external interrupt signal, the control circuit 21 sends a request for power supply to the CPU 10 to the power IC 200. Since the CPU 10 in the state where power supply is shut off is initialized, it takes a long boot time when power supply is resumed. For example, a boot time takes as long as 20 to 30 seconds in some cases. Further, since the control circuit 21 is configured by hardware, it can only execute a fixed sequence and cannot deal with a complex power supply sequence. For example, it is difficult for the control circuit 21 to execute a complex power supply sequence of detecting an external interrupt signal, turning on the power of the logic circuit A 30, remaining standby for 50 μs after executing an initialization routine of the logic circuit A 30, and then turning on the power of the CPU 10. Even if such a complex power supply sequence can be executed by the hardware fixed circuit, it is not possible to execute another power supply sequence without preparation. Furthermore, placing the circuits for executing various types of power supply sequences on a hardware fixed circuit increases the circuit size.
An example of the conventional power control technique is disclosed in Japanese Unexamined Patent Publication No. 2002-341976. The integrated circuit disclosed therein implements CPU power control by a control circuit placed in an I/O terminal. However, this control circuit merely performs very simple control and a backup register also merely performs backup of each signal. Therefore, this control circuit cannot execute a complex power supply sequence and is not flexible.
Another example of the conventional power control technique is disclosed in Japanese Unexamined Patent Publication No. 2002-288150. The integrated circuit disclosed therein has both a high performance CPU and a low power consumption CPU and shuts off the power supply to the CPU that is not operating, thereby reducing leakage current and power consumption. However, since the CPU has an arithmetic circuit, a considerable amount of leakage current occurs in spite of low power consumption and the effect of reducing power consumption is small.
As described in the foregoing, it has now been discovered that the conventional integrated circuit device cannot deal with a complex power supply sequence since it implements CPU power control with a hardware fixed circuit. Further, the conventional technique that implements high performance CPU power control with a low power consumption CPU has only a small power consumption reduction effect.